Members

Li Hengjie (李恒杰): CPU design, IO design, graphs, and documentation
Zhang Wencheng (张闻城): CPU design
Zhang Qi (张琦): assembly code

Github Repository

https://github.com/ZephyrusZhang/CS202-Final-HW-Pipellined-CPU

Roadmap

A record of the team’s working roadmap:

If there is anything that can be worked on better, or something not right in the code, raise an issue or comment on this page to help us improve. Thanks in advance.

Software

Designed with VIVADO, and additional files:

<aside> 📁 Files

Translates Minisys ISA set instructions to machine code in .coe files

Merges instruction and data .coe files into one .txt file for UART transmission

Used to send the .txt file through UART to the development board

[Script from this site ← (highly recommend)](https://s3-us-west-2.amazonaws.com/secure.notion-static.com/7b21873f-079c-451b-9b15-01c80b5e047c/converter.py)

Script from this site ← (highly recommend)

The IP core used by the UART module

</aside>

Hardware Specifications

This CPU design is developed on the Xilinx Artix-7TM series FPGA, development board model XC7A100T FGG484C-1.

<aside> 📁 Files

Some documentations for this development board are provided below:

Minisys Hardware Manual 1.1 (Chinese).pdf

Block Memory Generator Product Guide.pdf

FPGA XC7A100T 2FGG676.pdf

FPGA XC7A100T FGG484 Package.webarchive

</aside>

The dev board might differ, please check the following hardware specifications and adjust the parameters accordingly (the parameters will be given here in the Parameters section).

Clocks

Y18 pin provides a 100 MHz oscillator, which will be translated into 4 different clock signals by using 4 clk_generator modules
- clk_cpu used throughout the entire CPU, set to 100 MHz
- clk_vga is set to 25 MHz to match the requirements of a VGA display
- clk_uart is set to 10MHz to match the requirements of the UART port
- clk_tube is set to tick every 1 ms for the seven segment tubes to refresh

Switches

W4 switch is used for resetting the system, with input of +3.3V or +1.8V and a bit width of 1 bit
Y9, W9, Y7, Y8, AB8, AA8, V8, V9 switches are used for user input during IO interrupts, input will be in binary format and stored into the lower 8 bits of a 32 bit register

Keys

Key A will be used to pause and resume the execution of the CPU
- default state of the CPU will be EXECUTE
- press to pause
- press again to resume
Key B will be used to toggle the input between keypad and switches
- default input device will be keypad
- press to change input from keypad to switches
- press again to change from switches to keypad
Key C and D will not be utilized
Keys 1, 2, 3, 4, 5, 6, 7, 8, 9 will be used for user input during IO interrupts, input will be in decimal format and stored into a 32 bit register
Key * will be used for backspace, each press will clear the least recent input from the keypad, if the user have not keyed in any valid data (data that is greater than 0 is considered valid), then it will have no effect on the segment tube display
Key # will be used for enter, which specifies that the user have completed the data input, and the resulting data will be a 32 bits binary with padded zeros
K4, J4, L3, K3 are input pins for rows 1 to 4 respectively
M2, K6, J6, L5 are output pins for columns 1 to 4 respectively
The wiring for the pins to the keypad is shown in Graph 0

Graph 0 (Minisys Hardware Manual 1.1)